The combined pixel signal obtained by combining the signal from the pixel 10 (1, 1) and the signal from the pixel 10 (3, 1) will be input via the first vertical signal line VL1 and the switch SW1 to the capacitor 51 in the arithmetic unit 50. The pixel signal from the pixel 10 (2, 1) at the central position will be input via the second vertical signal line VL2 and the switch SW2 to the capacitor 52 in the arithmetic unit 50. The arithmetic unit 50 will then output, through the output terminal 63, a pixel signal (sum pixel signal) obtained by adding together and averaging the combined pixel signal having been input to the capacitor 51 and the pixel signal from the pixel 10 (2, 1) at the central position having been input to the capacitor 52. The sum pixel signal output through the output terminal 63 will be a signal generated by combining the signals from the pixel 10 (1, 1), the pixel 10 (2, 1) and the pixel 10 (3, 1).