The arithmetic unit 50b includes the first input unit Ia through sixth input unit If, capacitors 51 through 57, switches SW51 through SW59 and switches SW61 through SW66. One terminal of the capacitor 51 is connected to the first vertical signal line VL1a via the switch SW61 and another terminal of the capacitor 51 is connected to an input terminal 62 of an amplification unit 60. One terminal of the capacitor 52 is connected to the second vertical signal line VL2a via the switch SW62 and another terminal of the capacitor 52 is connected to the input terminal 62. One terminal of the capacitor 53 is connected to the first vertical signal line VL1b via the switch SW63 and another terminal of the capacitor 53 is connected to the input terminal 62, whereas one terminal of the capacitor 54 is connected to the second vertical signal line VL2b via the switch SW64 and another terminal of the capacitor 54 is connected to the input terminal 62. One terminal of the capacitor 55 is connected to the first vertical signal line VL1c via the switch SW65 and another terminal of the capacitor 55 is connected to the input terminal 62, whereas one terminal of the capacitor 56 is connected to the second vertical signal line VL2c via the switch SW66 and another terminal of the capacitor 56 is connected to the input terminal 62. In addition, one terminal of the capacitor 57 is connected to the input terminal 62 of the amplification unit 60 and another terminal of the capacitor 57 is connected to an output terminal 63 of the amplification unit 60. The capacitance at the capacitor 53 takes a capacitance value C, whereas the capacitances at the capacitors 51 through 56 all assume a capacitance value which is ? of the capacitance value C, i.e., a capacitance value ? C. It is to be noted that the capacitors 51 through 57 may be each constituted with a variable capacitor having a variable capacitance value.