In addition, as the switch SW54 enters an ON state, the pixel signal from the pixel 10 (2, 2) having been output on the second vertical signal line VL2b is input to the capacitor 54 and the capacitor 56. The combined pixel signal derived from the pixel 10 (1, 1) and the pixel 10 (3, 1) having been output on the first vertical signal line VL1a is input to the capacitor 51. The combined pixel signal derived from the pixel 10 (2, 1) and the pixel 10 (2, 3) having been output on the second vertical signal line VL2a and the second vertical signal line VL2c is then input to the capacitor 52. Furthermore, the combined pixel signal derived from the pixel 10 (1, 2) and the pixel 10 (3, 2) having been output on the first vertical signal line VL1b is input to the capacitor 53, and the combined pixel signal derived from the pixel 10 (1, 3) and the pixel 10 (3, 3) having been output on the first vertical signal line VL1c is input to the capacitor 55.