Switching converter, control circuit and control method thereof
地域：
Hangzhou
摘要
A method of controlling a switching converter having a plurality of interleaved parallel branches, can include controlling conduction phases of power switches of the plurality of interleaved parallel branches to be overlapped when a load changes from a light load to a heavy load, in order to improve dynamic response performance of the switching converter. A control circuit for a switching converter with a plurality of interleaved parallel branches, can control conduction phases of power switches of the interleaved parallel branches to be overlapped when a load changes from a light load to a heavy load, in order to improve dynamic response performance of the switching converter.
說明書
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This application claims the benefit of Chinese Patent Application No. 201811101457.6, filed on Sep. 20, 2018, which is incorporated herein by reference in its entirety.
The present invention generally relates to the field of power electronics, and more particularly to switching converters, and associated control circuits and methods.
A switched-mode power supply (SMPS), or a “switching” power supply, can include a power stage circuit and a control circuit. When there is an input voltage, the control circuit can consider internal parameters and external load changes, and may regulate the on/off times of the switch system in the power stage circuit. Switching power supplies have a wide variety of applications in modern electronics. For example, switching power supplies can be used to drive light-emitting diode (LED) loads.
權(quán)利要求
What is claimed is:1. A method of controlling a switching converter having a plurality of interleaved parallel branches, the method comprising:a) controlling conduction phases of power switches of the plurality of interleaved parallel branches to be overlapped when a load changes from a light load to a heavy load, in order to improve dynamic response performance of the switching converter; b) determining a turn-on moment of the power switch of each interleaved parallel branch in accordance with a compensation signal and a ripple signal, wherein the compensation signal is configured to characterize a difference between an output voltage of the switching converter and an expected value of the output voltage, and the ripple signal is obtained in accordance with the output voltage and voltages at intermediate nodes of each of the interleaved parallel branches; c) shielding on-time control signals corresponding to each interleaved parallel branch when the compensation signal is continuously greater than the ripple signal; and d) controlling the power switches of remaining interleaved parallel branches to be turned on when a time that the compensation signal is continuously greater than the ripple signal is greater than a predetermined time threshold. 2. The method of claim 1 , further comprising controlling the conduction phases of the power switches of the plurality of interleaved parallel branches not to be overlapped when the switching converter operates in a steady state to reduce ripple. 3. The method of claim 1 , wherein when the load changes from the light load to the heavy load, at least one on-time control signal of corresponding branch is disabled to achieve simultaneous conduction control for at least two power switches. 4. The method of claim 1 , further comprising controlling the power switches corresponding to the plurality of interleaved parallel branches to be turned on in a predetermined order, in accordance with a comparison result of the compensation signal and the ripple signal. 5. The method of claim 2 , further comprising:a) controlling on-time of the power switch of a master interleaved parallel branch to be a constant time in the steady state; and b) controlling on-time of the power switches of each of slave interleaved parallel branches in accordance with difference between an inductor current of each slave interleaved parallel branch and an inductor current of the master interleaved parallel branch correspondingly. 6. The method of claim 1 , further comprising:a) controlling the power switch of a master interleaved parallel branch in the remaining interleaved parallel branches to be turned on for a constant time; and b) controlling on-time of the power switches of each slave interleaved parallel branch in the remaining interleaved parallel branches in accordance with difference between an inductor current of each slave interleaved parallel branch and an inductor current of the master interleaved parallel branch correspondingly. 7. The method of claim 1 , further comprising controlling the power switch of which the on-time is greater than the predetermined time threshold to be turned off when the compensation signal is not greater than the ripple signal. 8. A control circuit for a switching converter, wherein the switching converter comprises a plurality of interleaved parallel branches, wherein the control circuit is configured to control conduction phases of power switches of the interleaved parallel branches to be overlapped when a load changes from a light load to a heavy load, in order to improve dynamic response performance of the switching converter, wherein the control circuit comprises:a) a plurality of shield circuits configured to shield on-time control signals corresponding to the power switches of each interleaved parallel branch when a set signal is active, such that the power switches of the interleaved parallel branches that are turned on remain to be turned on; b) a plurality of phase overlap circuits configured to generate an active phase overlap trigger signal after detecting that the on-time of the power switch of any interleaved parallel branch is greater than a predetermined time threshold; and c) a plurality of logic circuits, each of which corresponds to one interleaved parallel branch, and being configured to control the power switch of the corresponding interleaved parallel branch to be turned on after receiving the active phase overlap trigger signal. 9. The control circuit of claim 8 , wherein the control circuit is further configured to control the conduction phases of the power switches of the interleaved parallel branches not to be overlapped when the switching converter operates in a steady state, in order to reduce ripple. 10. The control circuit of claim 8 , comprising a set signal generating circuit configured to obtain a compensation signal and a ripple signal, and generate the set signal by comparing the compensation signal and the ripple signal, wherein the compensation signal is configured to characterize a difference between an output voltage of the switching converter and an expected value of the output voltage, and the ripple signal is obtained in accordance with the output voltage and voltages at intermediate nodes of each of the interleaved parallel branches. 11. The control circuit of claim 10 , further comprising a phase distribution circuit configured to control the power switches corresponding to the plurality of interleaved parallel branches to be turned on in a predetermined order in accordance with the set signal. 12. The control circuit of claim 10 , further comprising:a) a master on-time control circuit configured to control on-time of the power switch of a master interleaved parallel branch to be a constant time in a steady state; and b) a plurality of slave on-time control circuits, corresponding to each slave interleaved parallel branch, and configured to control on-time of the power switches of each slave interleaved parallel branch in accordance with difference between an inductor current of each slave interleaved parallel branch and an inductor current of the master interleaved parallel branch correspondingly. 13. The control circuit of claim 8 , wherein the shield circuit is configured not to shield when the set signal is inactive. 14. The control circuit of claim 8 , wherein each interleaved parallel branch is a buck topology. 15. The switching converter of claim 14 , wherein each interleaved parallel branch is a boost topology. 16. The switching converter of claim 14 , wherein each interleaved parallel branch is a buck-boost topology.
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