Referring now to FIG. 4, shown is a schematic circuit diagram of an example ramp signal generating circuit, in accordance with embodiments of the present invention. In this particular example, ramp signal generating circuit 131 can include resistors R1-R4, and capacitors C1 and C2. For example, one terminal of resistor R1 can connect to intermediate node x1 of master interleaved parallel branch 11, and the other terminal of resistor R1 can connect to intermediate node r1 of resistors R1 and R2. Resistor R2 can connect between intermediate node r1 and ground. Capacitor C1 can connect between intermediate node r1 and the output terminal of switching converter 1.

Thus, ramp signal Vr1 corresponding to master interleaved parallel branch 11 can be generated at intermediate node r1 according to voltage Vx1 at intermediate node x1 and output voltage Vout via resistors R1 and R2 and capacitor C1. One terminal of resistor R3 can connect to intermediate node x2 of salve interleaved parallel branch 12, and the other terminal of resistor R3 can connect to intermediate node r2 of resistors R3 and R4. Resistor R4 can connect between intermediate node r2 and ground. Capacitor C2 can connect between intermediate node r2 and the output terminal of switching converter 1. Also, ramp signal Vr2 corresponding to slave interleaved parallel branch 12 can be generated at intermediate node r2 according to voltage Vx2 of intermediate node x2 and output voltage Vout via resistors R3 and R4 and capacitor C2.