Alternatively, compensation circuit 32 can be a capacitor. Adder 31 can superimpose ramp signal Vr1 corresponding to master interleaved parallel branch 11 and ramp signal Vr2 corresponding to slave interleaved parallel branch 12 to generate a ripple signal (e.g., Error?). Comparator cmp1 can compare ripple signal Error? and compensation signal Error+ to generate set signal set. In this example, ramp signal Vr1 is a signal obtained based on the output voltage of the switching converter and voltage Vx1 at intermediate node x1 of master interleaved parallel branch 11. Ramp signal Vr2 can be a signal obtained based on the output voltage of the switching converter and voltage Vx2 at intermediate node x2 of slave interleaved parallel branch 12.

In this particular example, a non-inverting input terminal of error amplifier gm1 can receive reference signal Vref1, and an inverting input terminal of error amplifier gm1 may receive feedback signal Vfb. In other examples, the inverting input terminal of error amplifier gm1 can receive reference signal Vref1, and the non-inverting input terminal can receive feedback signal Vfb, which can also achieve substantially the same effect. Ramp signal generating circuit 131 can generate a corresponding ramp signal based on the output voltage of switching converter 1 and the voltage at the intermediate node of the corresponding interleaved parallel branch.