The apparatus may include additional components that perform each of the blocks of the algorithm in the aforementioned flowcharts of FIGS. 12-15. As such, each block in the aforementioned flowcharts of FIGS. 12-15 may be performed by a component and the apparatus may include one or more of those components. The components may be one or more hardware components specifically configured to carry out the stated processes/algorithm, implemented by a processor configured to perform the stated processes/algorithm, stored within a computer-readable medium for implementation by a processor, or some combination thereof.
FIG. 17 is a diagram 1700 illustrating an example of a hardware implementation for an apparatus 1602′ employing a processing system 1714. The processing system 1714 may be implemented with a bus architecture, represented generally by the bus 1724. The bus 1724 may include any number of interconnecting buses and bridges depending on the specific application of the processing system 1714 and the overall design constraints. The bus 1724 links together various circuits including one or more processors and/or hardware components, represented by the processor 1704, the components 1604, 1606, 1608, 1610, 1612, 1614, 1616, 1618, and 1620, and the computer-readable medium/memory 1706. The bus 1724 may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.
