FIG. 20 is a diagram 2000 illustrating an example of a hardware implementation for an apparatus 1902′ employing a processing system 2014. The processing system 2014 may be implemented with a bus architecture, represented generally by the bus 2024. The bus 2024 may include any number of interconnecting buses and bridges depending on the specific application of the processing system 2014 and the overall design constraints. The bus 2024 links together various circuits including one or more processors and/or hardware components, represented by the processor 2004, the components 1904, 1906, 1908, 1910, and the computer-readable medium/memory 2006. The bus 2024 may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.
