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Sounding reference signals with collisions in asymmetric carrier aggregation

專利號(hào)
US11159289B2
公開日期
2021-10-26
申請(qǐng)人
QUALCOMM Incorporated(US CA San Diego)
發(fā)明人
Alberto Rico Alvarino; Wanshi Chen; Peter Gaal; Jing Sun; Hao Xu; Srinivas Yerramalli
IPC分類
H04L5/00; H04L5/14; H04W72/04; H04W56/00
技術(shù)領(lǐng)域
srs,ue,uplink,cc,downlink,may,ccs,enb,subframe,in
地域: CA CA San Diego

摘要

An apparatus may use inactive uplink portions of a downlink CC to transmit SRS to an eNB. At times there may be a collision between the SRS transmission and uplink transmissions or downlink transmissions on another CC. The apparatus receives a carrier aggregation configuration for a first downlink CC and a second CC, determines to transmit an uplink transmission on the second CC or to receive a downlink transmission on the second CC, determines that the SRS would at least partially collide with the uplink transmission or the downlink transmission, and determines to adjust at least one of the uplink transmission, the SRS transmission, or reception of the downlink transmission based on the determination of the collision and an interruption time to transmit the SRS in the uplink portion of the first CC.

說明書

Several aspects of telecommunication systems will now be presented with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.

By way of example, an element, or any portion of an element, or any combination of elements may be implemented as a “processing system” that includes one or more processors. Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on a chip (SoC), baseband processors, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. One or more processors in the processing system may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.

權(quán)利要求

1
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