The terminal processor 801 may control to: receive, from the BS, first CORESET configuration information including first DMRS configuration information for a first CORESET; receive, from the BS, second CORESET configuration information including second DMRS configuration information for a second CORESET; identify a third CORESET, in which the first CORESET and the second CORESET overlap each other, based on the first CORESET configuration information and the second CORESET configuration information; and receive a DMRS based on the first DMRS configuration information in the first CORESET including the third CORESET. When the second CORESET is decoded, the terminal processor 801 may assume that a DMRS, which is based on the second DMRS configuration information, is not allocated to the second CORESET including the third CORESET. The first DMRS configuration information may correspond to a configuration of transmission of a DMRS in an entire band of the first CORESET, and the second DMRS configuration information may correspond to a configuration in which, in the second CORESET, a DMRS is transmitted only on a region for transmission of control information. Further, the terminal processor 801 may control to: perform blind-decoding based on a DMRS depending on the first DMRS configuration information in the first CORESET including the third CORESET; and perform blind-decoding based on a DMRS depending on the second DMRS configuration information in the second CORESET except for the third CORESET.

FIG. 9 is a block diagram illustrating a configuration of a BS according to embodiments of the disclosure.

As illustrated in FIG. 9, the BS according to the disclosure may include a BS processor 901, a BS receiver 902, and a BS transmitter 903.