Passive multi-input comparator for orthogonal codes on a multi-wire bus
地域：
Lausanne
摘要
Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.
說明書
This application is a continuation of U.S. application Ser. No. 16/435,412, filed Jun. 7, 2019, entitled “Passive Multi-Input Comparator for Orthogonal Codes on a Multi-Wire Bus,” which claims the benefit of U.S. Provisional Application No. 62/684,538, filed Jun. 13, 2018, entitled “Passive Multi-Input Comparator for Orthogonal Codes on a Multi-Wire Bus”, and claims the benefit of U.S. Provisional Application No. 62/683,955, filed Jun. 12, 2018, entitled “Passive Multi-Input Comparator for Orthogonal Codes on a Multi-Wire Bus”, all of which are hereby incorporated by reference in their entirety for all purposes.
The following prior applications are herein incorporated by reference in their entirety for all purposes:
U.S. Pat. No. 9,288,089, filed May 20, 2010 as application Ser. No. 12/784,414 and issued Mar. 15, 2016, naming Harm Cronie and Amin Shokrollahi, entitled “Orthogonal Differential Vector Signaling”, hereinafter identified as [Cronie].
U.S. patent application Ser. No. 13/842,740, filed Mar. 15, 2013, naming Brian Holden, Amin Shokrollahi, and Anant Singh, entitled “Methods and Systems for Skew Tolerance in and Advanced Detectors for Vector Signaling Codes for Chip-to-Chip Communication”, hereinafter identified as [Holden].
U.S. Pat. No. 9,100,232, filed Feb. 2, 2015 as application Ser. No. 14/612,241, and issued Aug. 4, 2015, naming Ali Hormati, Amin Shokrollahi, and Roger Ulrich, entitled “Method for Code Evaluation using ISI Ratio”, hereinafter identified as [Hormati I].
權利要求
We claim:1. An apparatus comprising:a plurality of wires of a multi-wire bus configured to carry signals corresponding to symbols of a codeword of a vector signaling code; an interconnected resistor network connected to the plurality of wires of the multi-wire bus, the interconnected resistor network configured to receive the signals corresponding to the symbols of the codeword of the vector signaling code and to responsively generate combinations of the symbols of the codeword of the vector signaling code at a plurality of output nodes, the plurality of output nodes grouped into a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels; a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes and configured to generate a respective sub-channel output of a plurality of sub-channel outputs; and a plurality of mode-selection transistors configured to selectively decouple one or more wires from one or more output nodes of the plurality of output nodes. 2. The apparatus of claim 1 , wherein each combination of the symbols of the codeword corresponds to an average of a respective two symbols of the codeword. 3. The apparatus of claim 1 , wherein each output node of the plurality of output nodes is connected to a respective two or more wires of the plurality of wires of the multi-wire bus, each wire of the respective two or more wires connected via a respective resistor of a plurality of resistors of the interconnected resistor network. 4. The apparatus of claim 3 , wherein the plurality of resistors each have equal impedance values. 5. The apparatus of claim 3 , wherein each resistor of the plurality of resistors has a tunable impedance. 6. The apparatus of claim 5 , wherein each resistor of the plurality of resistor comprises a parallel-resistor network configured to selectively enable one or more resistors in the parallel-resistor network to set a value of the tunable impedance. 7. The apparatus of claim 5 , wherein the interconnected resistor network is configured to adjust the tunable impedance to adjust high-frequency peaking of sub-channel outputs of the interconnected resistor network. 8. The apparatus of claim 1 , further comprising a mode controller configured to generate a set of control signals for the plurality of mode-selection transistors. 9. The apparatus of claim 1 , wherein the plurality of mode-selection transistors are configurable to operate in a plurality of operational modes selected from the group consisting of: orthogonal differential vector signaling mode, differential legacy mode, and transmit (Tx) mode. 10. The apparatus of claim 1 , wherein the plurality of mode-selection transistors are configured to couple one respective wire of the plurality of wires of the multi-wire bus to a respective output node of the plurality of output nodes, and wherein each sub-channel output of the plurality of sub-channel outputs corresponds to a differential output across two wires of the plurality of wires of the multi-wire bus. 11. A method comprising:receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code; generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes comprising a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels; generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes; and selecting an operational mode via a plurality of mode-selection transistors, the plurality of mode-selection transistors selectively decoupling one or more wires from one or more output nodes of the plurality of output nodes. 12. The method of claim 11 , wherein generating the plurality of combinations of the symbols of the codeword comprises adding a respective two or more signals corresponding to a respective two or more symbols of the codeword. 13. The method of claim 11 , wherein generating the plurality of combinations of the symbols of the codeword comprises forming an average of a respective two or more signals corresponding to a respective two or more symbols of the codeword. 14. The method of claim 11 , wherein each output node of the plurality of output nodes is connected to a respective two or more wires of the plurality of wires of the multi-wire bus, each wire of the respective two or more wires connected via a respective resistor of a plurality of resistors. 15. The method of claim 14 , wherein the plurality of resistors each have equal impedance values. 16. The method of claim 14 , wherein each resistor of the plurality of resistors has a tunable impedance. 17. The method of claim 16 , wherein each resistor of the plurality of resistor comprises a parallel-resistor network, and wherein the method further comprises selectively enabling one or more resistors in the parallel-resistor network to set an impedance value of the tunable impedance. 18. The method of claim 16 , further comprising adjusting high-frequency peaking of the plurality of sub-channel outputs by adjusting the tunable impedance. 19. The method of claim 11 , wherein the operational mode is selected from the group consisting of: orthogonal differential vector signaling mode, differential legacy mode, and transmit (Tx) mode. 20. The method of claim 11 , further comprising coupling one respective wire of the plurality of wires of the multi-wire bus to a respective output node of the plurality of output nodes, and wherein each sub-channel output of the plurality of sub-channel outputs corresponds to a differential output across two wires of the plurality of wires of the multi-wire bus.
意見反饋