FIG. 1 is a block diagram of a sub-channel receiver configured for detecting sub-channel Sub0, in accordance with some embodiments. In FIG. 1, the wire signals are labeled W0, W1, W2, W3, corresponding to the symbols of the codeword A, B, C, D of, in this example, sub-channel Sub0 defined by Eqn. 2. In at least one embodiment, the wire signals are received without additional amplification or signal processing. In other embodiments, the wire signals may be the outputs of conventional variable gain amplifiers (VGA), continuous-time linear equalizers (CTLE), or other active processing elements.