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Passive multi-input comparator for orthogonal codes on a multi-wire bus

專利號(hào)
US11159350B2
公開(kāi)日期
2021-10-26
申請(qǐng)人
Kandou Labs, S.A.(CH Lausanne)
發(fā)明人
Armin Tajalli; Chen Cao; Kiarash Gharibdoust
IPC分類
H04L25/02
技術(shù)領(lǐng)域
sub0,sub,resistor,channel,odvs,wire,in,codeword,w0,enrz
地域: Lausanne

摘要

Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.

說(shuō)明書(shū)

FIG. 1 is a block diagram of a sub-channel receiver configured for detecting sub-channel Sub0, in accordance with some embodiments. In FIG. 1, the wire signals are labeled W0, W1, W2, W3, corresponding to the symbols of the codeword A, B, C, D of, in this example, sub-channel Sub0 defined by Eqn. 2. In at least one embodiment, the wire signals are received without additional amplification or signal processing. In other embodiments, the wire signals may be the outputs of conventional variable gain amplifiers (VGA), continuous-time linear equalizers (CTLE), or other active processing elements.

權(quán)利要求

1
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