Identical filtering circuits 120 and 121, shown here as being composed of elements Rs and Cs, connected to a termination resistor Rt, provides frequency-dependent filtering and signal termination, in accordance with some embodiments. In one example embodiment, the combination of input series impedance (e.g. R1 paralleled with R3, etc.), Rs, and Cs provide a high frequency peaking effect. while Rt provides a termination impedance for the input signal. Such filtering may be useful for clock and data recovery or CTLE, where rounded (e.g., low-pass filtered) transitions are desirable to use transition samples for generating a phase-error signal used to update a voltage-controlled oscillator (VCO). The CDR disclosed in [Hormati II] utilizing DFE may benefit from such filtering to provided more rounded eyes when utilizing speculative DFE samples as phase error information. In some embodiments, by adjusting the impedances of resistors R1-R4, the cutoff frequency of the low-pass filter may be adjusted, as described in more detail below with respect to FIG. 3.

In one embodiment, 131 is a differential linear amplifier performing the subtraction operation of Eqn. 2, thus sub-channel output Sub₀ is an analog signal representing a respective data signal provided to the transmitter. In another embodiment, 131 is a differential comparator performing the subtraction operation by generating an analog antipodal value followed by an amplitude slicing operation, resulting in a binary digital sub-channel output corresponding to the binary data value used to modulate the sub-channel. In further embodiments, 131 may additionally incorporate clocked or dynamic sampling elements, capturing the state of the analog or digital result at a desired time.