Typically, switches S1, S2, S3, S4 are implemented using MOS transistors controlled by digital mode control signals e.g., a,b,c,d as well known in the art. The schematics of FIGS. 4-6 exemplify such embodiments. In some environments multiple-transistor transmission gates may be preferred instead of MOS transistors to provide additional signal headroom or reduced distortion. The sub-channel receivers of FIG. 1 and the resistor networks in FIGS. 4-6 include switches for supporting multiple modes of operation, however, some embodiments may omit such switches by shorting the terminals connected to the switches, such as the interconnected resistor network of FIG. 2.

Sub-channel receivers for subchannels Sub₁ and Sub₂ may be identical to FIG. 1 except for the order in which wire signals are connected to input resistors. As illustrated in FIG. 5, Sub₁ combines wire signals corresponding to symbols on wires W0 and W3 be combined to produce interim signal Sub₁⁺ and W1 and W2 be combined to produce Sub₁^?. Similarly, FIG. 6 illustrates that wire signals corresponding to symbols on wires W2 and W3 produce Sub₂⁺, and W0 and W1 to produce Sub₂^?.