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Passive multi-input comparator for orthogonal codes on a multi-wire bus

專利號
US11159350B2
公開日期
2021-10-26
申請人
Kandou Labs, S.A.(CH Lausanne)
發(fā)明人
Armin Tajalli; Chen Cao; Kiarash Gharibdoust
IPC分類
H04L25/02
技術領域
sub0,sub,resistor,channel,odvs,wire,in,codeword,w0,enrz
地域: Lausanne

摘要

Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.

說明書

FIGS. 4-6 illustrate resistor and switching networks for sub-channels Sub0-2, respectively. As shown, each resistor network receives mode control signals to control corresponding switches. In the following example, all three sub-channel receivers may operate in either an ODVS mode where wire signals are combined on pairs of sub-channel output nodes, or alternatively a “l(fā)egacy” mode may be initiated, in which sub-channel receivers Sub0 and Sub1 are configured to receive respective differential pairs signals, and sub-channel receiver Sub2 is turned off (e.g., disconnected from the bus). Table I below defines two such operation modes. In the first mode, all switches are enabled, and the pairs of sub-channel output nodes produce sub-channel outputs corresponding to detected ODVS sub-channels in accordance with Eqns. 2-4 described above. In the second mode, switches controlled by mode control signals a and c are enabled, and all other switches are disabled. In such an embodiment, a differential output between the wire signals on wires W1 and W0 is generated on the pair of sub-channel output nodes associated with sub-channel Sub0 and a differential output between the wire signals on wires W3 and W2 is generated on the pair of sub-channel output nodes associated with sub-channel Sub 1. FIG. 7 illustrates the interconnected resistor network of FIG. 2 additionally including the mode selection switches for enabling multi-mode operation. In a third mode, or Tx mode, the entire interconnected resistor network is disconnected to isolate the receive circuitry, and transmit drivers are connected to the wires. In a fourth mode, or full duplex mode, the interconnected resistor network is connected to two wires of the multi-wire bus to obtain a differential signal, while the remaining two wires may be connected to transmit drivers to transmit a differential signal. Table I below and FIGS. 9-10 illustrate such further modes.

權利要求

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