In some embodiments, as described above, the interconnected resistor network is part of a transceiver that includes multiple drivers for driving symbols onto the wires of the multi-wire bus. In such an embodiment, the drivers and interconnected resistor network may be selectively connected to the multi-wire bus in a Tx mode, or one of the multiple Rx modes described above, e.g., ODVS and differential signaling or “l(fā)egacy” mode. FIG. 9 is a block diagram of a transceiver 900, in accordance with some embodiments. As shown, the transceiver 900 includes a plurality of transmit drivers 905, and an interconnected resistor network 915 as previously described. In some embodiments, transceiver 900 may further include an encoder (not shown) configured to receive a set of input data and to responsively provide control signals to the drivers to generate the symbols of the codeword of the vector signal code on the multi-wire bus. The transceiver further includes a mode controller 920 that may be used to provide the multi-bit mode control signal based on a selected mode. In the transceiver 900 of FIG. 9, the multi-bit mode control signal is composed of 8 signals a-h used to control the switches in interconnected resistor network 915 as described above and shown in FIG. 7, as well as four additional signals i, j, k, l that are provided to a set of driver switches 910. In some embodiments, each signal i-l may be provided to a respective driver switch that is configured to connect or disconnect a corresponding driver to the corresponding wire of the multi-wire bus. Specifically, signal i may be provided to the driver associated with wire W0; signal j may be provided to the driver associated with wire W1; signal k may be provided to the driver associated with wire W2; and signal 1 may be provided to the driver associated with wire W3. Table I includes two additional modes utilizing such driver mode control signals. In a full Tx mode, the interconnected resistor network 915 may be fully disconnected from the multi-wire bus, while each driver is connected to a respective wire, and wire signals are driven onto the multi-wire bus. In some embodiments, a full-duplex mode may be configured, in which an inbound differential signal received via wires W0 and W1 is compared, and outbound signals are transmitted on wires W2 and W3 via the corresponding transmit drivers. Such an embodiment may utilize additional mode control signals, as control signals a and c would not be re-usable in the configuration shown in FIG. 7. In such embodiments, the MOS switches connecting wires W2 and W3 to sub-channel output nodes Sub1? and Sub1+ respectively, may receive control signals m and n. FIG. 10 illustrates a configuration of driver switches 910 utilizing 4 mode control signals i-l and an interconnected resistor network 1015 utilizing 10 mode control signals a-h, m, n for operating in such a full-duplex mode.
