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Passive multi-input comparator for orthogonal codes on a multi-wire bus

專利號
US11159350B2
公開日期
2021-10-26
申請人
Kandou Labs, S.A.(CH Lausanne)
發(fā)明人
Armin Tajalli; Chen Cao; Kiarash Gharibdoust
IPC分類
H04L25/02
技術領域
sub0,sub,resistor,channel,odvs,wire,in,codeword,w0,enrz
地域: Lausanne

摘要

Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.

說明書

FIG. 8 is a flowchart of a method 800, in accordance with some embodiments. As shown, method 800 includes receiving 802 a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code. A plurality of combinations of the symbols of the codeword of the vector signaling code are generated 804 using an interconnected resistor network connected to the plurality of wires of the multi-wire bus. The plurality of combinations of the symbols of the codeword of the vector signaling code are generated on a plurality of output nodes, where the plurality of output nodes are grouped to form a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels. A plurality of sub-channel outputs are generated 806 using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.

In some embodiments, the plurality of combinations of the symbols of the codeword are generated by adding two or more signals corresponding to the symbols of the codeword. In some embodiments, the plurality of combinations of the symbols of the codeword are generated by forming an average of two or more signals corresponding to the symbols of the codeword.

權利要求

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