In some embodiments, each output node of the plurality of output nodes is connected to two or more wires of the plurality of wires of the multi-wire bus via respective resistors of a plurality of resistors, as shown in FIG. 2. In some embodiments, the plurality of resistors have equal impedance values. In some embodiments, each resistor of the plurality of resistors has a tunable impedance, as shown in FIG. 3. In the parallel-resistor network of FIG. 3, the method further includes selectively enabling one or more resistors in the parallel-resistor network to set an impedance value of the tunable impedance. Some such embodiments include receiving a multi-bit impedance control signal at the parallel-resistor network, where the multi-bit impedance control signal is indicative of the impedance value of the tunable impedance. In some embodiments, adjusting the tunable impedance adjusts high-frequency peaking of the plurality of sub-channel outputs, which may be useful in CDR and CTLE applications.

In some embodiments, the method further includes selecting an operational mode via a plurality of mode-selection transistors, the plurality of mode-selection transistors selectively coupling/decoupling one or more wires to/from one or more output nodes of the plurality of output nodes. Some such embodiments may include coupling one respective wire of the plurality of wires of the multi-wire bus to a respective output node of the plurality of output nodes. In such embodiments, each sub-channel output of the plurality of sub-channel outputs corresponds to a differential output across two wires of the plurality of wires of the multi-wire bus, as previously described in the “l(fā)egacy” mode of operation.