where wire signals W0, W1, W2, W3 represent individual columns [Holden] further teaches that these equations may be efficiently implemented in analog logic as three instances of a four-input differential amplifier, the described embodiment having multiple transistor inputs producing two inverting and two non-inverting terms of equal weight that are actively summed to the desired result.

MIC embodiments that rely on active input elements may have issues with signal dynamic range and/or common mode rejection. The latter may be a significant problem with ODVS codes such as ENRZ, as modulation of one subchannel can present as a varying common mode offset in other sub-channels.

A passive MIC embodiment is presented which avoids these issues. Rather than using active circuit components to buffer and isolate the input signals before the analog computation, a passive interconnected resistor network performs the combinations of the symbols of the codeword on a plurality of pairs of sub-channel output nodes prior to a conventional differential signal receiver or amplifier. In at least one embodiment, an interconnected resistor network may include three identical instances of a resistor network each being driven by a respective input permutation of input signals to provide differential outputs on a respective pair of sub-channel output nodes that are provided to respective signal receivers/differential amplifiers, which in turn generate three sub-channel outputs. FIG. 1 is a schematic of one particular sub-channel receiver for detecting one sub-channel of the example ENRZ code, in accordance with some embodiments.