Scheduling request transmission control method and related product
摘要
說明書
The processing unit 602 may be a processor or a controller, which may be, for example, a Central Processing Unit (CPU), a universal processor, a Digital Signal Processor (DSP), an Application-Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or another programmable logical device, transistor logical device, hardware component or any combination thereof. It may implement or execute various exemplary logical blocks, modules and circuits described in combination with the contents disclosed in the disclosure. The processor may also be a combination realizing a calculation function, for example, including a combination of one or more microprocessors and a combination of a DSP and a microprocessor. The communication unit 603 may be a transceiver, a transceiver circuit and the like. The storage unit 601 may be a memory.
When the processing unit 602 is a processor, the communication unit 603 is a communication interface and the storage unit 601 is a memory, the terminal involved in the embodiment of the disclosure may be the terminal shown in
