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Host-based transfer of input-output operations from kernel space block device to user space block device

專利號
US11175840B2
公開日期
2021-11-16
申請人
EMC IP Holding Company LLC(US MA Hopkinton)
發(fā)明人
Sanjib Mallick; Md Haris Iqbal; Kundan Kumar
IPC分類
G06F9/54; G06F3/06; G06F9/50
技術(shù)領(lǐng)域
io,storage,mpio,submission,kernel,balancing,space,host,array,in
地域: MA MA Hopkinton

摘要

An apparatus in one embodiment comprises a host device comprising a processor coupled to memory. The host device is configured to communicate over a network with at least one storage system. The host device is further configured to generate a user space block device and to generate a kernel space block device corresponding to the user space block device. The host device is further configured to receive an input-output operation at the kernel space block device from an application executing on the host device and to transfer the input-output operation from the kernel space block device to the corresponding user space block device. The host device is further configured to submit the input-output operation to the at least one storage system based at least in part on the user space block device.

說明書

Although in some embodiments certain commands used by the host devices 102 to communicate with the storage array 105 illustratively comprise SCSI commands, other types of commands and command formats can be used in other embodiments. For example, some embodiments can implement IO operations utilizing command features and functionality associated with NVM Express (NVMe), as described in the NVMe Specification, Revision 1.3, May 2017, which is incorporated by reference herein. Other storage protocols of this type that may be utilized in illustrative embodiments disclosed herein include NVMe over Fabric, also referred to as NVMeoF.

The storage array 105 in the present embodiment is assumed to comprise a persistent memory that is implemented using a flash memory or other type of non-volatile memory of the storage array 105. More particular examples include NAND-based flash memory or other types of non-volatile memory such as resistive RAM, phase change memory, spin torque transfer magneto-resistive RAM (STT-MRAM) and Intel Optane? devices based on 3D XPoint? memory. The persistent memory is further assumed to be separate from the storage devices 106 of the storage array 105, although in other embodiments the persistent memory may be implemented as a designated portion or portions of one or more of the storage devices 106. For example, in some embodiments the storage devices 106 may comprise flash-based storage devices, as in embodiments involving all-flash storage arrays.

權(quán)利要求

1
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