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Write management of flash memory

專利號(hào)
US11175841B2
公開日期
2021-11-16
申請(qǐng)人
Silicon Motion, Inc.(TW Hsinchu County)
發(fā)明人
Jian-Dong Du; Chia-Jung Hsiao; Tsung-Chieh Yang
IPC分類
G06F3/06; G06F12/02
技術(shù)領(lǐng)域
erased,spare,pool,blocks,writing,controller,block,flash,command,in
地域: Hsinchu County

摘要

A method for use in management of a flash memory module is provided. The flash memory module has a plurality of blocks, wherein a portion of the blocks belong to a spare pool. The method includes: preserving at least one erased block in the spare pool for a write operation; monitoring an erasing period regarding the at least one erased block; and performing a replacement operation to replace the at least one erased block when the erase time exceeds a threshold.

說明書

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Moreover, a feature of the present invention is about how the controller 120 controls the flash memory module 130, which can be referred to FIG. 4. FIG. 4 is a diagram illustrating the interactions between a main control commands and a memory-operating command according to an embodiment of the present invention. When the host device 200 issues a main control command (e.g. a read command or a write command) to the controller 120, the controller 120 may access the flash memory chips 130_1-130_N in the flash memory module 130 according to the access types, addresses and related data comprised in the main control command and converting the above information into a corresponding memory-operating command.

In the present invention, the management on the erased block is independent from the main control command of the host device 200, and is performed according to the timestamp of erased blocks. Hence, even if the host device 200 does not issue the main control command to the controller 120, events (such as an alternative operation of the erased blocks as well as the garbage collection operation) may still be triggered due to the timestamp of the erased blocks in the spare pool 138 exceeding the threshold. Hence, in an embodiment, the controller 120 may issue the following consecutive command sequences to the flash memory chip 130_1-130_N without receiving any access command from the host device 200:

權(quán)利要求

1
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