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Write management of flash memory

專利號(hào)
US11175841B2
公開日期
2021-11-16
申請(qǐng)人
Silicon Motion, Inc.(TW Hsinchu County)
發(fā)明人
Jian-Dong Du; Chia-Jung Hsiao; Tsung-Chieh Yang
IPC分類
G06F3/06; G06F12/02
技術(shù)領(lǐng)域
erased,spare,pool,blocks,writing,controller,block,flash,command,in
地域: Hsinchu County

摘要

A method for use in management of a flash memory module is provided. The flash memory module has a plurality of blocks, wherein a portion of the blocks belong to a spare pool. The method includes: preserving at least one erased block in the spare pool for a write operation; monitoring an erasing period regarding the at least one erased block; and performing a replacement operation to replace the at least one erased block when the erase time exceeds a threshold.

說(shuō)明書

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Initially, if the timestamp of an erased block exceeds a duration limit, Step 240 in the aforementioned process will be triggered to write to erased blocks. As mentioned above, writing to erased blocks may also trigger the garbage collection operation in the meantime. Hence, the first reading command in the aforementioned command sequence is to perform the garbage collection operation, in order to read data from the valid pages in the blocks DB0-DBK that located outside the spare pool 138. The readout data will later be transmitted to the controller 120 to be processed with error correction. Next, the processed data (i.e. the second written command in the aforementioned command sequence) will be written to erased blocks. Lastly, the flow goes to Step 250 to select another block from the spare pool to erase, as an alternative of the erased blocks, i.e. the third erase command in the aforementioned command sequence. As can be further seen from the timing diagram in bottom of FIG. 4, the main control command may trigger the controller 120 to generate associated the memory-operating command, but the controller 120 will remain periodically generating spontaneous memory-operating commands. Therefore, a feature of the present invention lies in that even if the host device 200 has not yet to issue an access command to the controller 120, the controller 120 can nonetheless spontaneously issue successive command sequences (such as those for reading, writing and erasing) to the flash memory module 130.

權(quán)利要求

1
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