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Distribution and execution of instructions in a distributed computing environment

專利號
US11175901B2
公開日期
2021-11-16
申請人
VMware, Inc.（US CA Palo Alto）
發(fā)明人
Dimitar Ivanov; Martin Draganchev; Bryan Paul Halter; Nikola Atanasov; James Harrison
IPC分類
G06F9/44; G06F8/65; G06F8/61; H04L29/08; H04L12/24; G06F9/455
技術(shù)領(lǐng)域
management,endpoint,example,blueprint,agent,or,repository,in,executor,deployment
地域： CA CA Palo Alto

摘要

Methods and apparatus for distribution and execution of instructions in a distributed computing environment are disclosed. An example method includes accessing, by executing an instruction with a processor implementing a management agent within a deployment environment, an indication of an instruction to be executed, the indication of the instruction to be executed provided by a management endpoint operated at a virtual appliance within the deployment environment. The instruction is retrieved from a repository. The repository is identified by the indication of the instruction to be executed. An instruction executor is directed to execute the instruction. The instruction is to cause the instruction executor to install an update to the management agent.

說明書

FIG. 9 is a block diagram of an example processor platform 900 capable of executing the instructions of FIG. 7 to implement the example management endpoint 340 of FIGS. 3A, 3B, 3C, 4, and/or 5. The processor platform 900 of the illustrated example includes a processor 912. The processor 912 of the illustrated example is hardware. For example, the processor 912 can be implemented by one or more integrated circuits, logic circuits, microprocessors or controllers from any desired family or manufacturer.

The processor 912 of the illustrated example includes a local memory 913 (e.g., a cache), and executes instructions to implement the example management agent interface 510, the example queue manager 520, and/or the example result interface 550. The processor 912 of the illustrated example is in communication with a main memory including a volatile memory 914 and a non-volatile memory 916 via a bus 918. The volatile memory 914 may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM) and/or any other type of random access memory device. The non-volatile memory 916 may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory 914, 916 is controlled by a memory controller.

The processor platform 900 of the illustrated example also includes an interface circuit 920. The interface circuit 920 may be implemented by any type of interface standard, such as an Ethernet interface, a universal serial bus (USB), and/or a PCI express interface.

權(quán)利要求

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