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Synchronization of concurrent computation engines

專利號
US11175919B1
公開日期
2021-11-16
申請人
Amazon Technologies, Inc.(US WA Seattle)
發(fā)明人
Ilya Minkin; Ron Diamant; Drazen Borkovic; Jindrich Zejda; Dana Michelle Vantrease
IPC分類
G06F9/30; G06F9/35; G06F13/28; G06F9/38; G06F9/52; G06N3/06
技術(shù)領(lǐng)域
checkpoint,engine,execution,register,ckpt1,engines,in,wait,value,can
地域: WA WA Seattle

摘要

Integrated circuit devices and methods for synchronizing execution of program code for multiple concurrently operating execution engines of the integrated circuit devices are provided. In some cases, one execution engine of an integrated circuit device may be dependent on the operation of another execution engine of the integrated circuit device. To synchronize the execution engines around the dependency, a first execution engine may execute an instruction to set a value in a register while a second execution engine may execute an instruction to wait for a condition associated with the register value.

說明書

In various examples, the processing engine array 510 uses systolic execution, in which data arrives at each processing engine 511 from different directions at regular intervals. In some examples, input data can flow into the processing engine array 510 from the left and weight values can be loaded at the top. In some examples weights and input data can flow from the left and partial sums can flow from top to bottom. In these and other examples, a multiply-and-accumulate operation moves through the processing engine array 510 as a diagonal wave front, with data moving to the right and down across the array. Control signals can be input at the left at the same time as weights 506, and can flow across and down along with the computation.

In various implementations, the number of columns in the processing engine array 510 determines the computational capacity of the processing engine array 510, and the number of rows determines the required memory bandwidth for achieving maximum utilization of the processing engine array 510. The processing engine array 510 can have, for example, 64 columns and 428 rows, or some other number of columns and rows.

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