Further, while the example of FIG. 6 describes an embodiment including three checkpoint registers associated with each execution engine, embodiments in accordance with the present disclosure are not limited to this implementation. For example, in some implementations, each execution engine may have one associated checkpoint register that may be remotely set by the other execution engines. One of ordinary skill in the art will appreciate that other variations are possible without departing from the scope of the present disclosure.
FIG. 7 is a block diagram illustrating an example of an integrated circuit device that includes local checkpoint registers and multiple execution engines that can have data inter-dependencies. The example of FIG. 7 illustrates an accelerator engine 702. In various examples, the accelerator engine 702 includes processing engine array 720, an activation 740 block, and/or a pooling 750 block as well as a DMA engine 770, which may be located outside the accelerator engine 702. The processing engine array 720, the activation 740 block, the pooling 750 block, and DMA engine 770 are examples of execution engines an operate as described with respect the corresponding execution engines in FIG. 5. Thus, their operation will not be repeated here.
