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Synchronization of concurrent computation engines

專利號
US11175919B1
公開日期
2021-11-16
申請人
Amazon Technologies, Inc.(US WA Seattle)
發(fā)明人
Ilya Minkin; Ron Diamant; Drazen Borkovic; Jindrich Zejda; Dana Michelle Vantrease
IPC分類
G06F9/30; G06F9/35; G06F13/28; G06F9/38; G06F9/52; G06N3/06
技術(shù)領(lǐng)域
checkpoint,engine,execution,register,ckpt1,engines,in,wait,value,can
地域: WA WA Seattle

摘要

Integrated circuit devices and methods for synchronizing execution of program code for multiple concurrently operating execution engines of the integrated circuit devices are provided. In some cases, one execution engine of an integrated circuit device may be dependent on the operation of another execution engine of the integrated circuit device. To synchronize the execution engines around the dependency, a first execution engine may execute an instruction to set a value in a register while a second execution engine may execute an instruction to wait for a condition associated with the register value.

說明書

At block 840 of the method, a checkpoint register and a checkpoint value may be assigned to the connection between the first node and the second node of the graph (e.g., the input data set). An instruction generation procedure may assign the checkpoint register and checkpoint value to the connection (i.e., the graph edge connecting the first and second nodes). The integrated circuit device can implement checkpoints using hardware registers. The assigned checkpoint value is set in the checkpoint register when instructions executed by the execution engine reach the connection (i.e., dependency) between the nodes. Hardware registers can have a small footprint on the chip die, and little circuitry is needed to write a register value or check a register value.

The instruction generation procedure may assign different checkpoint values for the same checkpoint register or may assign values for different checkpoint registers to dependency edges of the dataflow graph in order to implement the dependencies represented by the edges. A checkpoint register may be a fixed length, for example, 256 bits or another length. The assigned checkpoint values for each checkpoint register may be monotonically increasing values.

In order to maintain the order of operations having data and/or resource dependencies, at block 850 a first set of program code including a checkpoint set instruction may be generated for the first execution engine. The instructions in the first set of program code for performing the first operation may include the checkpoint set instruction as a last instruction in the first set of program code. The checkpoint set instruction may be an instruction to set a value (i.e., a checkpoint) associated with assigned to a dependency. The integrated circuit device can implement the checkpoint using a hardware register, e.g., a checkpoint register.

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