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Synchronization of concurrent computation engines

專(zhuān)利號(hào)
US11175919B1
公開(kāi)日期
2021-11-16
申請(qǐng)人
Amazon Technologies, Inc.(US WA Seattle)
發(fā)明人
Ilya Minkin; Ron Diamant; Drazen Borkovic; Jindrich Zejda; Dana Michelle Vantrease
IPC分類(lèi)
G06F9/30; G06F9/35; G06F13/28; G06F9/38; G06F9/52; G06N3/06
技術(shù)領(lǐng)域
checkpoint,engine,execution,register,ckpt1,engines,in,wait,value,can
地域: WA WA Seattle

摘要

Integrated circuit devices and methods for synchronizing execution of program code for multiple concurrently operating execution engines of the integrated circuit devices are provided. In some cases, one execution engine of an integrated circuit device may be dependent on the operation of another execution engine of the integrated circuit device. To synchronize the execution engines around the dependency, a first execution engine may execute an instruction to set a value in a register while a second execution engine may execute an instruction to wait for a condition associated with the register value.

說(shuō)明書(shū)

The example accelerator 900 further includes DRAM controllers 942a-942k for communicating with an external memory. The external memory is implemented, in this example, using DRAM 930. In the illustrated example, the accelerator 900 includes k DRAM controllers 942a-942k, each of which may be able to communicate with an independent set of banks of DRAM. In other examples, other types of RAM technology can be used for the external memory. The DRAM controllers 942a-942k can also be referred to as memory controllers.

In various examples, input data and/or program code for the accelerators 902a-902n can be stored in the DRAM 930. Different programs can cause the accelerator engines 902a-902n to perform different operations. For example, when one of the accelerators is a neural network accelerator, one program can configure the neural network accelerator to perform speech recognition while another program can configure the neural network accelerator to perform image recognition. In various examples, different accelerator engines 902a-902n can be programmed with different programs, so that each performs a different set of operations. In various examples, the processors 948a-948s can manage moving of program code from the DRAM 930 to the accelerator engines 902a-902n.

權(quán)利要求

1
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