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Synchronization of concurrent computation engines

專(zhuān)利號(hào)
US11175919B1
公開(kāi)日期
2021-11-16
申請(qǐng)人
Amazon Technologies, Inc.（US WA Seattle）
發(fā)明人
Ilya Minkin; Ron Diamant; Drazen Borkovic; Jindrich Zejda; Dana Michelle Vantrease
IPC分類(lèi)
G06F9/30; G06F9/35; G06F13/28; G06F9/38; G06F9/52; G06N3/06
技術(shù)領(lǐng)域
checkpoint,engine,execution,register,ckpt1,engines,in,wait,value,can
地域： WA WA Seattle

摘要

Integrated circuit devices and methods for synchronizing execution of program code for multiple concurrently operating execution engines of the integrated circuit devices are provided. In some cases, one execution engine of an integrated circuit device may be dependent on the operation of another execution engine of the integrated circuit device. To synchronize the execution engines around the dependency, a first execution engine may execute an instruction to set a value in a register while a second execution engine may execute an instruction to wait for a condition associated with the register value.

說(shuō)明書(shū)

In some examples, a software program that is using the accelerator 1060 to conduct inference can read the result from a conditional layer from the accelerator 1060 and/or from a storage location, such as in DRAM 1030. In these examples, the program can determine what action the neural network should take next. For example, the program can determine to terminate the inference. As another example, the program can determine to change the direction of the inference, which can be translated by lower level code and/or the neural network processor to a next layer to execute. In these and other examples, the execution flow of the neural network can be coordinate by software.

The DRAM 1030 is memory that is used by the host processor 1072 for storage of program code that the host processor 1072 is in the process of executing, as well as values that are being operated on. In some examples, the data for a neural network (e.g., weight values, instructions, and other data) can be all or partially stored in the DRAM 1030. DRAM is a common term for processor memory, and though DRAM is volatile memory, processor memory can be volatile and/or non-volatile. Though not illustrated here, the host system 1000 can include other volatile and non-volatile memories for other purposes. For example, the host system 1000 can include a Read-Only Memory (ROM) that stores boot code for booting the host system 1000 at power on, and/or Basic Input/Output System (BIOS) code.

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