Providing exception stack management using stack panic fault exceptions in processor-based devices
地域：
WA
WA Redmond
摘要
Providing exception stack management using stack panic fault exceptions in processor-based devices is disclosed. In this regard, a processor device defines a “stack panic fault exception” that may be raised upon execution of an exception handler store operation attempting to write state data into an exception stack, and provides a dedicated plurality of stack panic fault exception state registers in which stack panic fault exception state data may be saved. Upon detecting a first exception, the processor device transfers program control to an exception handler for the first exception. If a second exception occurs upon execution of a store operation in the exception handler, the processor device determines that the second exception should be handled as a stack panic fault exception, saves the stack panic fault exception state data in the stack panic fault exception state registers, and transfers program control to a stack panic fault exception handler.
說明書
The technology of the disclosure relates to exception handling in processor-based devices, and, more particularly, to exception stack management.
A primary function of processor-based devices is the execution of software processes or programs that comprise computer-executable instructions. Generally speaking, the particular sequence in which a processor-based device executes instructions may be determined either by the order of the instructions in the original software code (i.e., “program order”), or by branch instructions that may transfer program control to an instruction other than the next sequential instruction in program order. Additionally, circumstances may arise in which a special or anomalous condition (i.e., an “exception”) that occurs during execution of a software process requires special handling. In such cases, execution of the original software process may be suspended, and program control may be transferred to a set of instructions known as an “exception handler” to address or remedy the circumstances that gave rise to the exception. When the exception handler completes execution, program control may be returned to the original software process if the exception was successfully remedied, the software process may be terminated if the exception cannot be remedied, or the original software process may be suspended to allow another process to execute.
權(quán)利要求
What is claimed is:1. A processor-based device, comprising:a processor device comprising:an exception stack; and a plurality of dedicated stack panic fault exception state registers; the processor device configured to:detect a first exception while executing a software process; responsive to detecting the first exception, transfer program control to an exception handler corresponding to the first exception; execute a store operation within the exception handler to store state data in the exception stack; detect a second exception while executing the store operation; determine that the second exception should be handled as a stack panic fault exception; and responsive to determining that the second exception should be handled as a stack panic fault exception:save stack panic fault exception state data in the plurality of dedicated stack panic fault exception state registers; and transfer program control to a stack panic fault exception handler corresponding to the stack panic fault exception. 2. The processor-based device of claim 1 , wherein the processor device is configured to determine that the second exception should be handled as a stack panic fault exception by being configured to determine that the store operation is performed by a store instruction that comprises a custom opcode indicating that the store instruction raises a stack panic fault exception. 3. The processor-based device of claim 1 , wherein the processor device is configured to determine that the second exception should be handled as a stack panic fault exception by being configured to determine that the store operation is performed by a store instruction that comprises a custom bit indicator indicating that the store instruction raises a stack panic fault exception. 4. The processor-based device of claim 1 , wherein the processor device is configured to determine that the second exception should be handled as a stack panic fault exception by being configured to determine that the store operation is performed by a store instruction that comprises a custom operand indicating that the store instruction raises a stack panic fault exception. 5. The processor-based device of claim 1 , wherein the processor device is configured to determine that the second exception should be handled as a stack panic fault exception by being configured to determine that the store operation is performed by a store instruction that is among a first N store instructions within the exception handler, where N is a positive integer. 6. The processor-based device of claim 1 , wherein:the processor device further comprises a stack panic indicator; the processor device is configured to determine that the second exception should be handled as a stack panic fault exception by being configured to determine that the stack panic indicator is set; and the processor device is further configured to:further responsive to detecting the first exception, set the stack panic indicator; transfer program control back to the exception handler once the stack panic fault exception handler completes execution; and clear the stack panic indicator once the exception handler completes execution. 7. The processor-based device of claim 1 , wherein the processor device is further configured to transfer program control to the stack panic fault exception handler corresponding to the stack panic fault exception based on a stack panic fault exception vector of the processor device. 8. A method for providing exception stack management using stack panic fault exceptions, comprising:detecting, by a processor device of a processor-based device, a first exception while executing a software process; responsive to detecting the first exception, transferring program control to an exception handler corresponding to the first exception; executing a store operation within the exception handler to store state data in an exception stack of the processor device; detecting a second exception while executing the store operation; determining that the second exception should be handled as a stack panic fault exception; and responsive to determining that the second exception should be handled as a stack panic fault exception:saving stack panic fault exception state data in a plurality of dedicated stack panic fault exception state registers; and transferring program control to a stack panic fault exception handler corresponding to the stack panic fault exception. 9. The method of claim 8 , wherein determining that the second exception should be handled as a stack panic fault exception comprises determining that the store operation is performed by a store instruction that comprises a custom opcode indicating that the store instruction raises a stack panic fault exception. 10. The method of claim 8 , wherein determining that the second exception should be handled as a stack panic fault exception comprises determining that the store operation is performed by a store instruction that comprises a custom bit indicator indicating that the store instruction raises a stack panic fault exception. 11. The method of claim 8 , wherein determining that the second exception should be handled as a stack panic fault exception comprises determining that the store operation is performed by a store instruction that comprises a custom operand indicating that the store instruction raises a stack panic fault exception. 12. The method of claim 8 , wherein determining that the second exception should be handled as a stack panic fault exception comprises determining that the store operation is performed by a store instruction that is among a first N store instructions within the exception handler, where N is a positive integer. 13. The method of claim 8 , wherein:determining that the second exception should be handled as a stack panic fault exception comprises determining that the stack panic indicator is set; and the method further comprises:further responsive to detecting the first exception, setting the stack panic indicator; transferring program control back to the exception handler once the stack panic fault exception handler completes execution; and clearing the stack panic indicator once the exception handler completes execution. 14. The method of claim 8 , further comprising transferring program control to a stack panic fault exception handler corresponding to the stack panic fault exception based on a stack panic fault exception vector of the processor device. 15. A non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor, cause the processor to:detect a first exception while executing a software process; responsive to detecting the first exception, transfer program control to an exception handler corresponding to the first exception; execute a store operation within the exception handler to store state data in an exception stack; detect a second exception while executing the store operation; determine that the second exception should be handled as a stack panic fault exception; and responsive to determining that the second exception should be handled as a stack panic fault exception:save stack panic fault exception state data in a plurality of dedicated stack panic fault exception state registers of the processor; and transfer program control to a stack panic fault exception handler corresponding to the stack panic fault exception. 16. The non-transitory computer-readable medium of claim 15 , wherein the computer-executable instructions cause the processor to determine that the second exception should be handled as a stack panic fault exception by causing the processor to determine that the store operation is performed by a store instruction that comprises a custom opcode indicating that the store instruction raises a stack panic fault exception. 17. The non-transitory computer-readable medium of claim 15 , wherein the computer-executable instructions cause the processor to determine that the second exception should be handled as a stack panic fault exception by causing the processor to determine that the store operation is performed by a store instruction that comprises a custom bit indicator indicating that the store instruction raises a stack panic fault exception. 18. The non-transitory computer-readable medium of claim 15 , wherein the computer-executable instructions cause the processor to determine that the second exception should be handled as a stack panic fault exception by causing the processor to determine that the store operation is performed by a store instruction that comprises a custom operand indicating that the store instruction raises a stack panic fault exception. 19. The non-transitory computer-readable medium of claim 15 , wherein the computer-executable instructions cause the processor to determine that the second exception should be handled as a stack panic fault exception by causing the processor to determine that the store operation is performed by a store instruction that is among a first N store instructions within the exception handler, where N is a positive integer. 20. The non-transitory computer-readable medium of claim 15 , wherein:the computer-executable instructions cause the processor to determine that the second exception should be handled as a stack panic fault exception by causing the processor to determine that the stack panic indicator is set; and the computer-executable instructions further cause the processor to:further responsive to detecting the first exception, set the stack panic indicator; transfer program control back to the exception handler once the stack panic fault exception handler completes execution; and clear the stack panic indicator once the exception handler completes execution.
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