As noted above, it may be possible for a second exception to occur as a result of executing a store operation to store additional state data to the exception stack 138 within an exception handler that is executed to remedy a first exception. The occurrence of such a second exception could result in the exception state data that was saved in the exception state registers 134 being overwritten and lost, making it impossible to restore the processor-based device 100 to its original state prior to the first exception. Moreover, conventional approaches to addressing this issue require may additional processing and/or additional system resources that result in reduced processor performance and reduced system flexibility for the processor-based device 100.

In this regard, the processor device 102 of FIG. 1 is configured to define a new type of exception referred to herein as a “stack panic fault exception,” which may be raised by a store operation that is executed within an exception handler and that attempts to write state data into the exception stack 138. The processor device 102 is also configured to provide a dedicated plurality of stack panic fault exception state registers 144, in which exception state data associated with a stack panic fault exception may be saved. The dedicated plurality of stack panic fault exception state registers 144 may include registers corresponding in functionality to the exception state registers 134. For example, the dedicated plurality of stack panic fault exception state registers 144 may include a stack panic fault exception link register (SPFELR) that corresponds in functionality to the ELR of the exception state registers 134.