Upon detecting a first exception while executing a software process, the processor device 102 in some embodiments may save exception state data in the exception state registers 134 in conventional fashion. The processor device 102 is configured to then transfer program control to an exception handler corresponding to the first exception. If a second exception occurs upon execution of a store operation in the exception handler to the exception stack, the processor device determines that the second exception should be handled as a stack panic fault exception. In response to determining that the second exception should be handled as a stack panic fault exception, the processor device saves stack panic fault exception state data in the plurality of dedicated stack panic fault exception state registers 144, and then transfers program control to a stack panic fault exception handler. In this manner, the stack panic fault exception can be safely handled without the need for an additional instruction sequence(s) in the exception handler or additional system resources, and without losing the exception state data saved in the exception state registers 134 as a result of the first exception.