In some embodiments, the processor device 102 may determine that the second exception should be handled as a stack panic fault exception by determining that a store instruction that performed the store operation is “stack-panic-fault-enabled” based on characteristics of the store instruction. For example, the processor device 102 may determine that the store operation was performed by a store instruction that comprises a custom opcode, a custom bit indicator within a conventional opcode, or a custom operand along with a conventional opcode, wherein the custom opcode, the custom bit indicator, or the custom operand indicates that the store instruction raises a stack panic fault exception. Some embodiments may provide that the processor device 102 may determine that the second exception should be handled as a stack panic fault exception by determining that the store operation is performed by a store instruction that is within the first N store instructions within the exception handler, where N is a positive integer. In such embodiments, the value of N may be selected according to the requirements of each particular embodiment. For example, some embodiments may provide that N equals one (1), such that the processor device 102 determines that the second exception should be handled as a stack panic fault exception by determining that the store operation is performed by a store instruction that is the ordinal first store instruction to execute within the exception handler.