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Providing exception stack management using stack panic fault exceptions in processor-based devices

專利號
US11175926B2
公開日期
2021-11-16
申請人
Microsoft Technology Licensing, LLC(US WA Redmond)
發(fā)明人
Thomas Andrew Sartorius; Michael Scott McIlvaine; James Norris Dieffenderfer; Aaron S. Giles
IPC分類
G06F9/38; G06F9/30; G06F11/07
技術(shù)領(lǐng)域
exception,panic,stack,fault,handler,processor,store,device,in,registers
地域: WA WA Redmond

摘要

Providing exception stack management using stack panic fault exceptions in processor-based devices is disclosed. In this regard, a processor device defines a “stack panic fault exception” that may be raised upon execution of an exception handler store operation attempting to write state data into an exception stack, and provides a dedicated plurality of stack panic fault exception state registers in which stack panic fault exception state data may be saved. Upon detecting a first exception, the processor device transfers program control to an exception handler for the first exception. If a second exception occurs upon execution of a store operation in the exception handler, the processor device determines that the second exception should be handled as a stack panic fault exception, saves the stack panic fault exception state data in the stack panic fault exception state registers, and transfers program control to a stack panic fault exception handler.

說明書

As part of conventional exception handling, the processor-based device may first save exception state data into specialized registers referred to herein as exception state registers. The exception state registers may be used to save exception state data such as the value of a program counter at the time the exception occurred, as well as data related to the state of the processor-based device (e.g., processor mode, address translation settings, and the like, as non-limiting examples). Once program control is transferred to the exception handler, additional state data that may be required to preserve or restore the state of the processor-based device (e.g., the current values of general purpose registers (GPRs) and/or floating point registers (FPRs), as non-limiting examples) must be expressly stored by the exception handler in a data structure known as an exception stack. Thus, one of the first functions performed by the exception handler is the execution of one or more store operations to write the additional state data into the exception stack (either by executing a store instruction, or by the processor-based device automatically performing the store operation to the exception stack without actually executing a store instruction). However, in some scenarios it may be possible for a further exception to occur as a result of executing the store operations to the exception stack within the exception handler. The occurrence of such a second exception could result in the exception state data that was saved to the exception state registers as a result of the first exception being overwritten and lost, making it impossible to restore the processor-based device to its original state.

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