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Providing exception stack management using stack panic fault exceptions in processor-based devices

專利號
US11175926B2
公開日期
2021-11-16
申請人
Microsoft Technology Licensing, LLC(US WA Redmond)
發(fā)明人
Thomas Andrew Sartorius; Michael Scott McIlvaine; James Norris Dieffenderfer; Aaron S. Giles
IPC分類
G06F9/38; G06F9/30; G06F11/07
技術(shù)領(lǐng)域
exception,panic,stack,fault,handler,processor,store,device,in,registers
地域: WA WA Redmond

摘要

Providing exception stack management using stack panic fault exceptions in processor-based devices is disclosed. In this regard, a processor device defines a “stack panic fault exception” that may be raised upon execution of an exception handler store operation attempting to write state data into an exception stack, and provides a dedicated plurality of stack panic fault exception state registers in which stack panic fault exception state data may be saved. Upon detecting a first exception, the processor device transfers program control to an exception handler for the first exception. If a second exception occurs upon execution of a store operation in the exception handler, the processor device determines that the second exception should be handled as a stack panic fault exception, saves the stack panic fault exception state data in the stack panic fault exception state registers, and transfers program control to a stack panic fault exception handler.

說明書

In another exemplary embodiment, a non-transitory computer-readable medium having stored thereon computer-executable instructions is provided. The computer-executable instructions, when executed by a processor, cause the processor to detect a first exception while executing a software process. The computer-executable instructions further cause the processor to, responsive to detecting the first exception, transfer program control to an exception handler corresponding to the first exception. The computer-executable instructions also cause the processor to execute a store operation within the exception handler to store state data in an exception stack. The computer-executable instructions additionally cause the processor to detect a second exception while executing the store operation. The computer-executable instructions further cause the processor to determine that the second exception should be handled as a stack panic fault exception. The computer-executable instructions also cause the processor to, responsive to determining that the second exception should be handled as a stack panic fault exception, save stack panic fault exception state data in a plurality of dedicated stack panic fault exception state registers of the processor, and transfer program control to a stack panic fault exception handler corresponding to the stack panic fault exception.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional embodiments thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

權(quán)利要求

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