The accompanying drawing figures incorporated in and forming a part of this specification illustrate several embodiments of the disclosure, and together with the description serve to explain the principles of the disclosure.

FIG. 1 is a block diagram illustrating an exemplary processor-based device configured to providing exception stack management using stack panic fault exceptions;

FIG. 2 is a diagram illustrating exemplary operations for handling a stack panic fault exception occurring as a result of an attempt to store state data in an exception stack, according to some embodiments;

FIG. 3A-3C are block diagrams illustrating exemplary embodiments of a stack-panic-fault-enabled store instruction, according to some embodiments;

FIGS. 4A-4C provide a flowchart illustrating exemplary operations of the processor-based device of FIG. 1 for providing exception stack management using stack panic fault exceptions, according to some embodiments; and

FIG. 5 is a block diagram of an exemplary processor-based device, such as the processor-based device of FIG. 1, that is configured to provide exception stack management using stack panic fault exceptions, according to some embodiments.