Exemplary embodiments disclosed herein include providing exception stack management using stack panic fault exceptions in processor-based devices. In one exemplary embodiment, a processor-based device includes a processor device that defines a new type of exception referred to herein as a “stack panic fault exception.” A stack panic fault exception is an exception that may be raised by a store operation that is executed within an exception handler and that attempts to write state data into an exception stack. The processor device also provides a dedicated plurality of stack panic fault exception state registers in which exception state data associated with a stack panic fault exception may be saved. Upon detecting a first exception while executing a software process, the processor device in some embodiments may save exception state data in exception state registers in conventional fashion, and then transfer program control to an exception handler corresponding to the first exception. If a second exception occurs upon execution of a store operation in the exception handler to the handler stack, the processor device determines that the second exception should be handled as a stack panic fault exception (e.g., based on a custom opcode, custom bit indicator, or a custom operand of the store instruction that performed the store operation; by determining that the store operation is performed by a store instruction that is among a first N store instructions within the exception handler, where N is a positive integer; or by determining that a stack panic indicator is set, as non-limiting examples). In response to determining that the second exception should be handled as a stack panic fault exception, the processor device saves stack panic fault exception state data in the plurality of dedicated stack panic fault exception state registers. In some embodiments, the processor device may then transfer program control to a stack panic fault exception hander. In this manner, the stack panic fault exception can be safely handled without the need for an additional instruction sequence(s) in the exception handler or additional system resources, and without losing the exception state data saved as a result of the first exception.