Fast boot
摘要
說明書
Due to physical hardware boundaries, a physical processor cannot directly address every guest physical address. When a guest physical address needs to be read or written, it is translated into a physical address that the physical processor can access.
In one embodiment, this is handled through the physical processor's second level page tables. When software makes a reference to a guest (virtual) physical address, if the page of memory containing that address is resident on the node that has the processor that generated that address, the address is represented in the second level page table. Automatic address translation hardware will then translate that address to a guest physical address and then to a real physical address as it normally does by using the first and second level page tables, with no performance degradation. However, if the memory address is not present in the second level page table, the hardware cannot completely translate that guest address to a real physical address, and the processor generates an interrupt. The hyper-kernel fields that interrupt and analyzes the request (similar to what an operating system might do when it needs to copy a page that is not memory-resident but is only resident on a backing store). This analysis may result in a request for that page to be sent (migrated) to the node from a different node, or it may result in a decision to migrate that virtual processor to the node that has that page of memory. Page reads and writes may be handled differently. For example, readable pages may be replicated, but a writable page requires additional overhead to remove that page from the L4 cache of other nodes that may have a copy (i.e., invalidation).
