白丝美女被狂躁免费视频网站,500av导航大全精品,yw.193.cnc爆乳尤物未满,97se亚洲综合色区,аⅴ天堂中文在线网官网

Fast boot

專利號
US11175927B2
公開日期
2021-11-16
申請人
TidalScale, Inc.(US CA Los Gatos)
發(fā)明人
David P. Reed; Isaac R. Nassi; Pete Jarvis
IPC分類
G06F9/44; G06F9/4401; G06F9/455; G06F9/48; G06F12/0815; H04L29/08; G06F12/1009
技術(shù)領(lǐng)域
page,node,dormant,tidalpod,memory,in,guest,nam,hyper,node_0
地域: CA CA Campbell

摘要

Initializing a computing system using dormant pages includes marking a set of guest physical addresses as dormant. It further includes, for each node in a plurality of physical nodes, designating a set of real physical addresses for zeroing. An operating system is executing collectively across the physical nodes.

說明書

In some embodiments, the network-attached memory 1306 is an array of memory (1312) (e.g., bytes of flash memory). The NAM also includes a processor (1314) configured to implement a cache coherency protocol, as described herein. Multiple NAMs may be used for redundancy and/or resiliency. In this example, the network-attached memory appliance 1306 is centrally located in a flash appliance accessible to all of the nodes in the cluster. In other embodiments, the network attached memory may be distributed in parts throughout the cluster, on one or more nodes (where examples of portions of the NAM distributed across nodes 1304 are shown at 1316-1322).

Using the techniques described herein, pages of memory may be placed in the NAM, just as pages of memory can be put on any node in the system, as described above (e.g., when performing memory migration). In some embodiments, the network-attached memory appliance communicates with the other nodes in the TidalPod over the interconnect using a cache coherency protocol, which will be described in further detail below.

FIG. 13B illustrates an example embodiment of a system in which a network-attached memory is used in selective resource migration. In this example, nodes 1352 and 1354 are examples of nodes 1304 and 458-462. As shown in this example, each node has a hyper-kernel. Also shown, is an example embodiment of a memory or cache hierarchy on each node, which include L1, L2, and L3 caches. Each node also includes DRAM, used as an L4 cache.

權(quán)利要求

1
微信群二維碼
意見反饋