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Microservices change management and analytics

專利號(hào)
US11175947B2
公開(kāi)日期
2021-11-16
申請(qǐng)人
INTERNATIONAL BUSINESS MACHINES CORPORATION(US NY Armonk)
發(fā)明人
Selcuk Nedim Oezmen; Clea Anne Zolotow; Ulrike Vauth
IPC分類
G06F21/57; G06F8/76; G06F9/448; G06F9/48; G06F11/14; G06F11/07; G06F9/54; G06F9/46; G06F11/36
技術(shù)領(lǐng)域
invocation,or,matrix,network,computer,in,cloud,process,computing,system
地域: NY NY Armonk

摘要

Managing microservice changes and performing related analytics can include generating a plurality of process instance representations. Each process instance representation can be generated based on a corresponding process path that comprises an ordered sequence of operations that are performed by a process using multiple microservices. A microservices network representation can be constructed based on the plurality of process instance representations, each element of the microservices network corresponding to an interface between a pair of the microservices. Based on the microservices network representation, a relative frequency can be determined for each of the microservices, each relative frequency corresponding to a likelihood that a change in a microservice will affect the performance of at least one process using at least one of the microservices.

說(shuō)明書(shū)

Program/utility 840 is executable by processor 816. Program/utility 840 and any data items used, generated, and/or operated upon by computer system 812 are functional data structures that impart functionality when employed by computer system 812. As defined within this disclosure, a “data structure” is a physical implementation of a data model's organization of data within a physical memory. As such, a data structure is formed of specific electrical or magnetic structural elements in a memory. A data structure imposes physical organization on the data stored in the memory as used by an application program executed using a processor.

Bus 818 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example only, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, Peripheral Component Interconnect (PCI) bus, and PCI Express (PCIe) bus.

權(quán)利要求

1
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