According to one embodiment, the set of computation units comprises a minimum number of computation units such that a logic utilization of the FPGA is higher than a predefined threshold. For the example, the logic utilization of the FPGA may be higher than 90%. Therefore, the silicon area of the FPGA may be used optimally.

According to one embodiment, the number of computation units of the set of computation units is the number of bits of the highest bit length of the set of bit lengths. For example, if the highest bit length is 8-bit, the set of computation units comprises 8 computation units. In one example, the set computation units are associated with bit lengths 8-bit, 7-bit, 6-bit, 5-bit, 4-bit, 3-bit, 2-bit, and 1-bit respectively. In this case, the controller has a step size of one. This may be advantageous as it covers all possible representations. In another example, the controller may have a step size of two such that the set computation units are associated with bit lengths 8-bit, 6-bit, 4-bit and 2-bit. This may be advantageous as it may lower the area occupied by the controller. In one example, the step size of the controller may be defined by a user. In another example, the step size may be determined by profiling the input data, and based on their statistic distributions, the controller's step size may be determined. For example, if 80% of the calculations involve numbers in the form of XXX0000X, then the step size may be defined accordingly.

According to one embodiment, the computation task is one of: training a deep neural network, inference of a deep neural network, matrix-vector multiplication, and matrix-matrix multiplication.