According to one embodiment, the input data of the operation comprises two operands of a multiplication. The controller comprises a cascade of logic gates to determine a maximum number of leading zeros that is present in the operands of the input data, wherein the maximum number of leading zeros is indicative of the bit length of the selected computation unit. The maximum number of leading zeros may be associated with a bit length that is higher than or equal to the bit length of the selected computation unit. This embodiment may provide a simplistic design of the controller (e.g., only logic gates may be used), which may lower the area and latency overhead of the controller.

For example, the set of commutation units comprises a computation unit associated with 8-bit and computation units associated with 3-bit and 5-bit. If the selected bit is 2-bit, then the computation unit associated with 3-bit or 5-bit may be selected, preferably the smallest of the two may be selected. If the selected bit is 4-bit, then the computation unit with 5-bit is selected since it is the only one having a bit length higher than 4-bit and smaller than 8-bit.

According to one embodiment, the controller and the set of computation units are configured to operate in pipeline order. This may enable high-throughput data processing.

According to one embodiment, the selected computation unit is associated with the smallest bit length that is smaller than or equal to the certain bit length.

A computation unit is associated with a bit length meaning that the computation unit may perform operations using operands or values of the input data that are represented by said bit length.

According to one embodiment, the certain bit length is the highest bit length of the set of bit lengths.