FIG. 1 is a block diagram of a hardware acceleration system 100 in accordance with an embodiment of the present invention. The hardware acceleration system 100 may be a heterogeneous processing system. For example, the hardware acceleration system 100 may comprise different types of processing units such as CPU, GPU, FPGA, ASICs, etc.

For simplification of the description, FIG. 1 shows a simplified configuration of a host computer 101 coupled to a hardware accelerator 102 that provides acceleration for processing data in comparison to processing data in software. However, it is not limited to that configuration and other configurations of the hardware acceleration system 100 may be used, e.g., a configuration involving multiple hardware accelerators coupled to a host computer may be used or a configuration involving only hardware accelerators may be used.

The hardware accelerator 102 may be connected to the host computer 101 through a PCI express bus or Ethernet connection. The host computer 101 may be configured to execute initial boot procedures, basic 110 functions, and so on. The host computer 101 may comprise a host processor 103, such as a CPU. The host processor 103 may be configured to access to data stored in an external disk 108 and data stored in a local host cache memory. The host processor 103 may communicate data via a network interface 109. The hardware accelerator 102 has an accelerator architecture that is optimized, with respect to the host computer architecture, for speeding up the execution of a particular class of computing functions. Such accelerated computing functions include, for example, vector processing and floating point operations.