Hardware accelerator for executing a computation task
摘要
說明書
For example, the hardware accelerator 102 may comprise a FPGA. The host processor 103 and the FPGA may be configured so as to execute or implement the computation task. The host processor 103 may be coupled to a memory 105 storing a compiled software application 107. The compiled software application 107 includes function calls. The FPGA coupled to the hardware processor may include a compiled user function. The compiled user function may be executable in response to one of the function calls. The function call may comprise a message of variables that need to be processed by the user function. The hardware accelerator may be coupled to memories such as off-chip memories 111 and on-chip memories 112 for storing, for example, intermediate computation results of the hardware accelerator.
