Each pair of the pairs of units may be connected to a controller 215 (also named speculative precision controller (SPC)). For each pair of the pairs, the controller 215 is configured to receive the input data represented with the highest bit length and to select one of the units of the pair that can deliver a valid result first, wherein the output of the selected unit is provided as a result of the operation. For example, for the pair of units comprising the computation unit 210A and replication unit 212A, the controller 215 is configured to receive the input data of the operation 201A, wherein the received input data are in precision A that corresponds to the highest bit length 8-bit. The controller 215 may select one of the two units 210A and 212A of the pair that can deliver a valid result first/earlier. The replication unit 212A may perform the operation 201A faster than the computation unit 210A because it uses data with less precision. The controller 215 may thus decide whether the result that is provided by the replication unit 212A is a valid result. For that, the controller may, for example, calculate the number of leading zeros on the operands of the input data of the data operation 201A (e.g., as described with reference to FIG. 4). As soon as the controller makes a decision, the results of the respective unit are forwarded, and the remaining speculated execution may be forced to cancel the calculation. The hardware accelerator 202 further comprises an on-chip memory 214, e.g., tensor on chip memory, for storing intermediate processing results and/or providing the necessary data to each computation unit every cycle.