The hardware accelerator 302 comprises a set of computation units 310.1 through 310.8. Each of the computation units 310.1 through 310.8 may, for example, be a General Matrix Multiply (GEMM) core of a FPGA. Each of the 8 computation units 310.1 through 310.8 is associated with a respective bit length. The computation unit 310.1 is associated with the bit length 1-bit. The computation unit 310.2 is associated with the bit length 2-bit. The computation unit 310.3 is associated with the bit length 3-bit. The computation unit 310.4 is associated with the bit length 4-bit. The computation unit 310.5 is associated with the bit length 5-bit. The computation unit 310.6 is associated with the bit length 6-bit. The computation unit 310.7 is associated with the bit length 7-bit. The computation unit 310.8 is associated with the bit length 8-bit. The expression “computation unit U is associated with the bit length lb” means that the computation unit U is configured to receive or process input data being represented with the bit length lb.