Each of the computation units 310.1 through 310.8 is configured to perform an operation (e.g., multiplication) of the two operands stored in the pair of input registers to which the computation unit is connected and to output the result of the operation into an output register to which the computation unit is connected. The computation unit 310.8 is connected to the 16-bit output register (named tensor register 16-bit). The computation unit 310.7 is connected to the 14-bit output register (named tensor register 14-bit). The computation unit 310.6 is connected to the 12-bit output register (named tensor register 12-bit). The computation unit 310.5 is connected to the 10-bit output register (named tensor register 10-bit). The computation unit 310.4 is connected to the 8-bit output register (named tensor register 8-bit). The computation unit 310.3 is connected to the 6-bit output register (named tensor register 6-bit). The computation unit 310.2 is connected to the 4-bit output register (named tensor register 4-bit). The computation unit 310.1 is connected to the 1-bit output register (named tensor register 1-bit).

The hardware accelerator 302 further comprises a controller 315 and a selector 317. The controller, also called the speculative precision controller, 315 is connected to the set of computation units 310.1 through 310.N and to the selector 317. The selector 317 is configured to receive data of the output registers. Although shown as separate components, the controller 315 and the selector 317 may, in another example, form an integral part.