The input data of each operation of the set of operations may be obtained from the matrices A and B using a direct memory access (DMA) that enables to load input data into the DMA loads 321 and 322. For example, the two operands of each operation may be loaded into the two DMA loads 321 and 322, respectively, before being stored in the pair of input registers with the highest bit length and before being provided as input to the controller 315. As shown in FIG. 3, the two operands of a given operation, e.g., OP1, are represented with the 8-bit representation and may first be stored in the pair of input 8-bit registers. In one example, the input registers of the remaining computation units 310.1 through 310.7 may have the same size as the number of bits of their associated bit length, e.g., the computation unit 310.7 may have a 7-bit wide register, etc. The 7 LSB bits of the two operands stored in the pair of input 8-bit registers are transferred to the pair of input 7-bit registers. The 6 LSB bits of the two operands stored in the pair of input 7-bit registers are transferred to the pair of input 6-bit registers. The 5 LSB bits of the two operands stored in the pair of input 5-bit registers are transferred to the pair of input 5-bit registers. The 4 LSB bits of the two operands stored in the pair of input 5-bit registers are transferred to the pair of input 4-bit registers. The 3 LSB bits of the two operands stored in the pair of input 4-bit registers are transferred to the pair of input 3-bit registers. The 2 LSB bits of the two operands stored in the pair of input 3-bit registers are transferred to the pair of input 2-bit registers. The 1 LSB bit of the two operands stored in the pair of input 2-bit registers are transferred to the pair of input 1-bit registers.