Hardware accelerator for executing a computation task
地域：
NY
NY Armonk
摘要
The present disclosure relates to a hardware accelerator for executing a computation task composed of a set of operations. The hardware accelerator comprises a controller and a set of computation units. Each computation unit of the set of computation units is configured to receive input data of an operation of the set of operations and to perform the operation, wherein the input data is represented with a distinct bit length associated with each computation unit. The controller is configured to receive the input data represented with a certain bit length of the bit lengths and to select one of the set of computation units that can deliver a valid result and that is associated with a bit length smaller than or equal to the certain bit length.
說明書
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Each pair of bits of the pairs (b7, c7), (b6, c6), (b5, c5), (b4, c4), (b3, c3), (b2, c2) and (b1, c1) may be input to a respective OR gate 401.1 through 401.7 of the controller 413. The outputs of the pair of OR gates 401.7 and 401.6 may be connected to an OR gate 403.6. The outputs of the pair of OR gates 403.6 and 401.5 may be connected to an OR gate 403.5. The outputs of the pair of OR gates 403.5 and 401.4 may be connected to an OR gate 403.4. The outputs of the pair of OR gates 403.4 and 401.3 may be connected to an OR gate 403.3. The outputs of the pair of OR gates 403.3 and 401.2 may be connected to an OR gate 403.2. The outputs of the pair of OR gates 403.2 and 401.1 may be connected to an OR gate 403.1.
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