Each of the OR gates 401.7 and 403.1 through 403.6 may be connected to a respective NOT gate 405.1 through 405.7. The output of each of the NOT gates 405.1 through 405.7 may be indicative of one of 1-bit, 2-bit, . . . 7-bit representations respectively. The 8-bit representation is associated with an output of a NOT gate 405.8 which receives value “1” as input. The controller 415 further comprises a selector 417 that is configured to receive the outputs of the NOT gates 405.1 through 405.8 and parse them from MSB to LSB in order to select the last signal/output with value “1”. If, for example, the selected signal is the one that corresponds to 3-bit representation, this indicates that the controller 415 may select the computation unit that is associated with the 3-bit representation to provide the result of the operation.

FIG. 5 is a diagram illustrating the execution flow of a give data operation in accordance with an embodiment of the present invention. In this example, the set of computation units comprises an 8-bit GEMM and 3-bit GEMM.